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pd-60325 i p2005apbf high frequency synchronous buck optimized lga power stage integrated power semiconduct ors, driver ic, & passives features 40a multiphase building block no de-rating up to t pcb = 95oc optimized for low power loss optimized for low emi bias supply range of 4.5v to 7.0v operation up to 1.5mhz bi-directional current flow under voltage lockout lga interface 7.65mm x 7.65mm outline description the ip2005a is a fully optimized solution for high current synchronous buck multiphase applications. board space and design time are greatly reduced because most of the components required for each phase of a typical discrete-based multiphase circuit are integrated into a single 7.65mm x 7.65mm x 1.66mm power block. the additional components required for a complete multiphase converter are a pwm controller, the output inductors, and the input and output capacitors. ipowir technology offers designers an innovative board space saving solution for applications requiring high power densities. ipowir technology eases design for applications where component integration offers benefits in performance and functionality. ipowir technology solutions are also optimized internally for layout, heat transfer, and component selection. applications high frequency, lo w profile dc-dc multi-phase architectures low duty cycle, high current solutions microprocessor power supplies general dc/ dc converters package description interface connection standard quantity t & r orientation ip2005apbf lga 10 n/a IP2005ATRPBF lga 2000 figure 15 2/8/2008 www.irf.com typical application 1 ip2005a product efficiency v in = 12v, f sw = 1mhz, & t blk = 125oc 70 72 74 76 78 80 82 84 86 88 90 92 94 4 6 8 10121416182022242628303234363840 efficiency (%) output current (a) vo ? = ? 3.3v vo ? = ? 2.5v vo ? = ? 1.8v vo ? = ? 1.3v downloaded from: http:///
pd-60325 i p2005apbf v in to p gnd ....-0.5v to 16.5v v dd to p gnd ...-0.5v to 7.5v cv cc to p gnd ........-0.5v to 7.5v pwm to p gnd .-0.5v to vdd + 0.5v (note 1) enable to p gnd ..-0.5v to vdd + 0.5v (note 1) storage temperature ..-60oc to 150oc block temperature .. -40oc to 150oc (note 2) esd rating....jedec, jesd22-a114 (hbm[4kv], class 3a) ..jedec, jesd22-a115 (mm[400v], class c) msl rating....3 reflow temperature ....260oc peak absolute maximum ratings (voltages referenced to p gnd ) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those listed in the recommended operating conditions section of th is specification is not implied. recommended operating conditions parameter min typ max units conditions supply voltage (v dd ) 4.5 - 7.0 v input voltage (v in ) 6.5 - 13.2 v output voltage (v out )- - 5 . 5 v output current (i out )- - 4 0 a switching frequency 250 - 1500 khz on time duty cycle - - 85 % minimum v sw on time 60 - - ns v dd = 5.0v, v in = 12v block temperature (t blk ) -40 - 125 oc (note 2) www.irf.com 2/8/2008 2 downloaded from: http:///
pd-60325 i p2005apbf electrical specifications these specifications apply for t blk = 0oc to 125oc and v dd = 5.0v unless otherwise specified. parameter min typ max units conditions p loss power block losses - 9.3 11.1 w v in = 12v, v dd = 5.0v, v out = 1.3v, i out = 40a, f sw = 1mhz, l out = 0.3uh, t blk = 25oc (note 3) v dd supply current (stand by) (i q-vdd ) -2 . 23m a v dd = 5.0, enable = 0v supply current (operating) - 50 65 ma v in = 12v, enable = v dd = 5v, f sw = 1mhz, 10% dc cv cc (ldo output) output voltage 5.5 6.0 6.75 v output current 80 - - ma output capacitor 1.0 - - f ceramic, x5r, 16v power-on reset (por) v dd rising 3.7 4.1 4.5 v hysteresis 140 185 230 mv v dd rising & falling cvcc rising 4.2 4.6 5.0 v hysteresis 165 220 275 mv cv cc rising & falling enable input logic level low threshold (v il )- - 0 . 8 v logic level high threshold (v ih ) 2.0 - - v threshold hysteresis - 100 - mv weak pull-down impedance - 100 - k ? rising propagation delay (t pdh ) -4 0-n s falling propagation delay (t pdl ) -7 5-n s schmitt trigger input v dd = por to 7.0v www.irf.com 2/8/2008 3 downloaded from: http:///
pd-60325 i p2005apbf 2/8/2008 www.irf.com 4 parameter min typ max units conditions pwm input logic level low threshold (v il )- - 0 . 8 v logic level high threshold (v ih ) 2.0 - - v threshold hysteresis - 100 - mv weak pull-down impedance - 100 - k ? rising propagation delay (t pdh ) -6 0-n s falling propagation delay (t pdl ) -3 0-n s schmitt trigger input v dd = por to 7.0v (note 4) electrical specifi cations (continued) these specifications apply for t blk = 0oc to 125oc and v dd = 5.0v unless otherwise specified. notes: 1. must not exceed 7.5v 2. block temperature (t blk ) is defined as any die temperature within the package 3. measurement made with six 10f (tdk c3225x5r1c106kt or equivalent) ceramic capacitors placed a cross vin to pgnd pins (see figure 8) 4. not associated with rise and fall times. does not affect power loss downloaded from: http:///
pd-60325 i p2005apbf power loss curve figure 1 power loss curve power loss (w) soa curve figure 2 safe operating area curve output current (a) www.irf.com 2/8/2008 5 downloaded from: http:///
pd-60325 i p2005apbf typical performance curves 2/8/2008 www.irf.com 6 figure 3 normalized power loss vs. input voltage power loss (normalized) figure 4 normalized power loss vs. output voltage 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 0.8 1.3 1.8 2.3 2.8 3.3 output voltage (v) -0.9 -0.5 0.0 0.5 0.9 1.4 1.9 2.3 2.8 3.3 3.7 4.2 v in = 12.0v v dd = 5.0v i out = 40a f sw = 1mhz l out = 300nh t blk = 125oc 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 6 7 8 9 10 11 12 13 14 input voltage (v) -2.4 -1.9 -1.4 -1.0 -0.5 0.0 0.5 1.0 1.4 1.9 2.4 soa temp adjustment (oc) v dd = 5.0v v out = 1.3v i out = 40a f sw = 1mhz l out = 300nh t blk = 125oc figure 5 normalized power loss vs. inductance figure 6 normalized power loss vs. switching frequency 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 250 500 750 1000 1250 1500 switching frequency (khz) -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 v in = 12.0v v dd = 5.0v v out = 1.3v i out = 40a l out = 300nh t blk = 125oc 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 output inductance (h) -1.0 -0.7 -0.5 -0.2 0.0 0.2 0.5 0.7 1.0 1.2 1.4 1.7 v in = 12.0v v dd = 5.0v v out = 1.3v i out = 40a f sw = 1mhz t blk = 125oc figure 7 v dd supply current vs. switching frequency average i dd (ma) downloaded from: http:///
pd-60325 i p2005apbf figure 8 power loss test circuit figure 9 timing diagram www.irf.com 2/8/2008 7 downloaded from: http:///
pd-60325 i p2005apbf applying the safe operating area (soa) curve the soa graph incorporates po wer loss and thermal resistance information in a way that allows one to solve for maximum current cap ability in a simplified graphical manner. it incorporates the ability to so lve thermal problems where heat is drawn out through the printed circuit board a nd the top of the case. please re fer to international rectifier application note an1047 for further details on using this soa cu rve in your thermal environment. procedure 1.calculate (based on estimate d power loss) or measure t he case temperature on the device and the board temp erature near the device (1mm from the edge). 2.draw a line from case temperature axis to the pcb temperature axis. 3.draw a vertical line from the t x axis intercept to the soa curve. 4.draw a horizontal line from th e intersection of the vertical line with the soa curve to the y- axis (output current). the point at which th e horizontal line meets the y-axis is the soa continuous current. v in = 12.0v v dd = 5.0v v out = 1.3v f sw = 1mhz l out = 300nh figure 10 soa example, continuous current 31a for t pcb = 100oc & t case = 110oc www.irf.com 2/8/2008 8 downloaded from: http:///
pd-60325 i p2005apbf calculating power loss and soa fo r different operating conditions to calculate power loss for a given set of operat ion conditions, the following procedure should be followed: power loss procedure 1.determine the maximum curre nt for each ip2005a and obt ain the maximum power loss from figure 1 2.use the normalized curv es to obtain power loss values th at match the operating conditions in the application 3.the maximum power loss under the application c onditions is then the product of the power loss from figure 1 and the normalized values. to calculate the safe operating area (soa) for a given set of op erating conditions, the following procedure should be followed: soa procedure 1.determine the maximum pcb and case temper ature at the maximu m operating current for each ip2005a 2.use the normalized curves to obtain soa temperature adjustments that match the operating conditions in the application 3.then, add the sum of the soa te mperature adjustments to the t x axis intercept in figure 2 design example operating conditions: output current = 30a input volt age = 10v output voltage = 1.3v switching freq = 750khz inducto r = 0.2h drive voltage (v dd ) = 5v calculating maximum power loss: (figure 1) maximum power loss = 9.0w (figure 3) normalized power loss for input voltage 0.95 (figure 4) normalized power loss for output voltage 1.0 (figure 5) normalized power loss for output inductor 1.026 (figure 6) normalized power loss for switch frequency 0.87 calculated maximum power loss 9.0w x 0.95 x 1. 0 x 1.026 x 0.87 7.63w www.irf.com 2/8/2008 9 downloaded from: http:///
pd-60325 i p2005apbf calculating so a temperature: (figure 3) soa temperature adjustment for input voltage -1.2oc (figure 4) soa temperature adjustment for output voltage 0.0oc (figure 5) soa temperature adj ustment for output inductor 0.6 oc (figure 6) soa temperature adj ustment for switch frequency -3.5 oc t x axis intercept adjustment -1.2 oc + 0.0 oc + 0.6 oc C 3.5 oc -4.1 oc assuming t pcb = 100oc & t case = 110oc the following example shows how t he soa current is adjusted for t x decrease of 4.1oc v in = 12.0v v dd = 5.0v v out = 1.3v f sw = 1mhz l out = 300nh 1. draw a line from case temperature axis to the pcb temperature axis. 2. draw a vertical line from the t x axis intercept to the soa curve. 3. draw a horizontal line from the intersection of the vertical line with the soa curve to the y-axis (output current). the point at which the horizontal line meets the y-axis is the soa continuous current. 4. draw a new vertic al line from the t x axis by adding or subtra cting the soa adjustment temperature from the original t x intercept point. 5. draw a horizontal line from the intersection of the new vertical li ne with the soa curve to the y-axis (output current). the point at which the horizont al line meets the y-axis is the new soa continuous current. the soa adjustment indicates the part is still allowed to run at a continuous current of 36a. www.irf.com 2/8/2008 10 downloaded from: http:///
2/8/2008 www.irf.com 11 pd-60325 i p2005apbf optimized emi feature 5v/div 20ns/div 5v/div 20ns/div vsw of ip2005a vsw of ip2003a the ip2005a is designed for lo w electromagnetic interference (emi) which minimizes power loss and space, and simplifies sy stem design by eliminating t he need for external snubber circuits. these benefits are ac hieved by optimizing the internal component layout, integrating bypass filters and implementing ac tive clamp circuitry as a means of reducing switching node voltage ringing; which is one of main sources of emi. t he figures above show waveform comparisons of switching node voltages of the previous generation ip2003a product and ip2005a under equivalent operation conditions. downloaded from: http:///
pd-60325 i p2005apbf internal block diagram figure 11 internal block diagram pin description pin number pin name description 1, 8 v in input voltage pin. connect input capacitors close to this pin. 2 vsw voltage switching node C pin connection to the output inductor. 3p gnd power ground 4v dd supply voltage to internal circuitry. 5p w m ttl level input to mosfet drivers. when pwm is high, the control fet is on and the sync fet is off. when pwm is low, the sync fet is on and the control fet is off. 6 enable when set to logic level high, internal circuitry of the device is enabled. when set to logic level low, the control and synchronous fets are turned off. 7c v cc output of internal regulator. at tached a minimum of 1.0f capacitance from this pin to pgnd. recommended to use 16v, x5r, ceramic type capacitor. www.irf.com 2/8/2008 12 downloaded from: http:///
pd-60325 i p2005apbf recommended pcb layout figure 12 top copper and solder-mask layer of pcb layout www.irf.com 2/8/2008 13 downloaded from: http:///
pd-60325 i p2005apbf figure 13 top & bottom component and via placement (topside, transparent view down) pcb layout guidelines the following guidelines are recommended to reduce the parasiti c values and optimize overall performance. ? all pads on the ip2005a footprint design need to be solder-mask defined (see figure 12). also refer to international rectifier app lication notes an1028 an d an1029 for further footprint design guidance. ? place as many vias ar ound the powe r pads (v in , v sw , and p gnd ) for both electrical and optimal therma l performance. ? a minimum of six 10f, x5r, 16v ceramic capacitors per ip2005a ar e needed for greater than 30a operation. this will result in the lowest loss due to input capacitor esr. ? placement of the ceramic input ca pacitors is critical to optimi ze switching performance. in cases where there is a heatsink on the case of ip2005a, place all si x ceramic capacitors right underneath the ip2005a footprint (s ee figure 13 bottom component layer). in cases where there is not heatsink, c1 and c6 on the bottom layer may be moved to the c1x and c6x locations (respectively) on th e top component layer (see figure 13 top component layer). in both cases, c2 C c5 need to be placed right underneath the ip2005a pcb footprint. ? dedicate at least two layer to for p gnd only ? duplicate the power nodes on mult iple layers (refer to an1029). www.irf.com 2/8/2008 14 downloaded from: http:///
pd-60325 i p2005apbf mechanical outline drawing electrical i/o bottom view 0.10 c 2x top view 5 4 side view bottom view corner id 0.10 c 2x 5 notes: 1. dimensions & tolerances per asme y14.5m C 1994 2. dimensions are shown in millimeters 3. tolerances are: .xx = +/- 0.1 .xxx = +/- 0.025 .xxxx = +/- 0.01 primary datum c is seating plane bilateral tolerance zone is appli ed to each side of package body layout notes: 1. land patterns on users pcb should be an identical mirror image of the pattern shown in bottom view 2. lands should be solder mask defined 3. all i/o pads on this product are metal finish with flash gold enable 6 cv cc 7 v in 8 v in 1 v sw 2 p gnd 3 v dd 4 pwm 5 45 figure 14 mechanical outline drawing www.irf.com 2/8/2008 15 downloaded from: http:///
pd-60325 i p2005apbf tape and reel information feed direction 12.00 (.473) 2005ap xxxx yymm 16.00 (.630) 2005ap xxxx yymm xx xx figure 15 tape and reel information www.irf.com 2/8/2008 16 downloaded from: http:///
pd-60325 i p2005apbf recommended solder paste stencil design notes: 1.this view is stencil squeegee view 2.dimensions are shown in millimeters 3.this opening is based on using 150 micron thick stencil. if usi ng a different thickness stencil, this opening needs to be adjusted accordingly. 4.dashed lines show stencil openings. solid lines show pcb pad openings. 5.the recommended reflow peak temperatur e is 260oc. the total furnace time is approximately 5 minutes with approximately 10 seconds at peak temperature. corner id figure 16 solder paste stencil design part marking figure 17 part marking www.irf.com 2/8/2008 17 downloaded from: http:///
pd-60325 i p2005apbf ir world headquarters: 101 n. sepulveda blvd., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed for the industrial market. visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 12/24/2007 www.irf.com 2/8/2008 18 downloaded from: http:///

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